1. Field of the Invention
This invention relates to high-performance computing network systems, and more particularly, to race conditions in parallel computing applications.
2. Description of the Relevant Art
High performance computing is often obtained by exploiting parallelism in a software application. With multiple processor cores (possibly thousands) in a high-performance computing network system, independent instructions of an application may be executed in parallel to increase throughput. For example, these processor cores may operate on a same line in memory, but on different data within the line. Upon the completion of these instructions, coherency checking is needed to ensure a race condition did not occur, or that two or more processors did not modify the same data within the memory line. Currently, complex software methodologies are used to detect race conditions. However, software techniques involve significant overhead and, therefore, incorporate a performance penalty.
In view of the above, effective methods and mechanisms for managing coherency in parallel processing systems is desired.